Semiconductor device and method for manufacturing semiconductor device

ABSTRACT

According to one embodiment, a semiconductor device includes a memory cell array including a first memory cell provided on a substrate and a second memory cell provided on the substrate. The memory cell array includes a charge storage layer provided on the substrate and a control electrode provided on the charge storage layer. A coupling ratio of the second memory cell is different from a coupling ratio of the first memory cell.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of U.S. patent application Ser. No.15/372,190, filed on Dec. 7, 2016, which is based upon and claims thebenefit of priority from U.S. Provisional Patent Application 62/304,730,filed on Mar. 7, 2016, the entire contents of each of which areincorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor deviceand a method for manufacturing a semiconductor device.

BACKGROUND

In a memory cell transistor (hereinafter referred to as a memory cell)including a control gate electrode and a charge storage layer such as afloating gate electrode, a coupling ratio (CR) between the control gateelectrode and the floating gate electrode is one of parameterscharacterizing a performance of a memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view exemplifying a planar layout of a majorelement in a semiconductor memory device of an embodiment;

FIG. 2A is a schematic cross-sectional view corresponding to A-A′section in FIG. 1, and FIG. 2B is a schematic cross-sectional viewcorresponding to B-B′ section in FIG. 1;

FIG. 3 is a schematic plan view of an arrangement example of a memorycell of the semiconductor memory device of the embodiment;

FIGS. 4A to 6B are schematic cross-sectional views showing a method formanufacturing the semiconductor memory device of the embodiment;

FIG. 7 is a schematic view explaining a mask used in the embodiment;

FIGS. 8A and 8B are schematic cross-sectional views showing a method formanufacturing the semiconductor memory device of the embodiment;

FIGS. 9A and 9B are schematic cross-sectional views showing a method formanufacturing a first example of the semiconductor memory device of theembodiment;

FIGS. 10A and 10B are schematic views explaining another example of themask of the embodiment;

FIG. 11 is a schematic plan view of a second example of thesemiconductor memory device of the embodiment;

FIG. 12 is a schematic plan view of a third example of the semiconductormemory device of the embodiment; and

FIG. 13 is a block diagram of a fourth example of a semiconductor deviceof the embodiment.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a memorycell array including a first memory cell provided on a substrate and asecond memory cell provided on the substrate. The memory cell arrayincludes a charge storage layer provided on the substrate and a controlelectrode provided on the charge storage layer. A coupling ratio of thesecond memory cell is different from a coupling ratio of the firstmemory cell.

Embodiments will now be described with reference to the drawings. Thesame components in the drawings are marked with the same referencenumerals. Although silicon is exemplified in the following embodimentsas a semiconductor, a semiconductor other than silicon may be used.

FIG. 1 is a schematic plan view of a semiconductor memory device of anembodiment.

The semiconductor memory device of the embodiment includes a memory cellarray 1. The memory cell array 1 includes a plurality of semiconductorregions (active regions) 11 and a plurality of control gate electrodes50. A planar layout of the semiconductor regions 11 and the control gateelectrodes 50 is shown in FIG. 1.

The semiconductor regions 11 extend in a Y-direction (first direction).The semiconductor regions 11 are separate from each other in aX-direction intersecting with the Y-direction. For example, theX-direction is substantively perpendicular to the Y-direction. Thecontrol gate electrodes 50 extend in the X-direction (second direction)different from the Y-direction. The control gate electrodes 50 areseparate from each other in the Y-direction intersecting with theY-direction. For example, the Y-direction is substantively perpendicularto the X-direction. The control gate electrodes 50 extend across thesemiconductor regions 11 in the X-direction above the semiconductorregions 11.

A memory cell MC described below is provided at an intersection of thesemiconductor region 11 and the control gate electrode 50. The memorycell array 1 includes a plurality of memory cells MC arrayed in theX-direction and the Y-direction.

FIGS. 2A and 2B are schematic cross-sectional views of the semiconductormemory device of the embodiment. FIG. 2A is a schematic cross-sectionalview corresponding to a part of A-A′ section in FIG. 1. FIG. 2B is aschematic cross-sectional view corresponding to a part of B-B′ sectionin FIG. 1. In FIGS. 2A and 2B, the positive direction of the Z-axis isupward, and the negative direction of the Z-axis is downward.

As shown in FIG. 2A, the fin-like semiconductor regions (active regions)11 extending in the Y-direction are formed on a major surface side ofthe substrate 10. The semiconductor regions 11 are separated in theX-direction by separation portions 60 having shallow trench isolation(STI) structure.

As shown in FIG. 2B, n⁺-type semiconductor regions (source/drainregions) 12 are provided in a surface of the semiconductor region 11.The semiconductor regions 12 are separated each other and arrayed in theY-direction. A p-type region (channel region) is formed between then⁺-type semiconductor regions 12 in the semiconductor region 11.

A first insulating film (gate insulating film, tunneling insulatingfilm) 20 is provided on the semiconductor region 11. The firstinsulating film 20 is, for example, a silicon oxide film. As shown inFIG. 2A, the first insulating film 20 is divided into a plurality in theX-direction by the separation portions 60. As shown in FIG. 2B, thefirst insulating film 20 continuously extends in the Y-direction.

A plurality of charge storage layers 30 is provided on the firstinsulating film 20. The charge storage layer 30 is a polysilicon filmdoped with, for example, phosphorus that is a dopant for a conductivepolysilicon. The charge storage layer 30 may be a silicon film dopedwith phosphorus and carbon. The charge storage layer 30 may containtungsten, titanium nitride, or tantalum nitride. As shown in FIGS. 2Aand 2B, the charge storage layers 30 are divided in the X-direction andthe Y-direction. As shown in FIG. 2B, the charge storage layers 30 aredivided in the Y-direction by insulating films 70. As shown in FIG. 2A,a portion 50 a of the control gate electrode 50 is provided between theadjacent charge storage layers 30 in the X-direction. A secondinsulating film 40 is provided between the portion 50 a of the controlgate electrode 50 and the charge storage layers 30. The charge storagelayer 30 is a floating gate electrode.

The second insulating film (interelectrode insulating film) 40 isprovided on the charge storage layer 30. The second insulating film 40is formed of a material having a dielectric constant higher than adielectric constant of the first insulating film 20. The secondinsulating film 40 is provided on the upper surface of the chargestorage layers 30. As shown in FIG. 2A, the second insulating film 40 isprovided also on the side surface in the X-direction of the chargestorage layers 30. The second insulating film 40 is continuous in theX-direction along the side surface and the upper surface of the chargestorage layers 30. As shown in FIG. 2B, the second insulating film 40 isdivided into a plurality in the Y-direction by the insulating films 70.The material of the second insulating film 40 is described below.

The control gate electrode 50 is provided on the second insulating film40. The control gate electrode 50 can be formed of the same material asthe charge storage layer 30 that is the floating gate electrode. Asshown in FIG. 1 and FIG. 2A, the control gate electrode 50 extends inthe X-direction. As shown in FIG. 1 and FIG. 2B, the control gateelectrode 50 is divided into a plurality in the Y-direction by theinsulating films 70. The control gate electrode 50 can be referred to asa word line.

As shown in FIG. 2A, the semiconductor region 11, the first insulatingfilm 20, and a lower portion of the charge storage layers 30 areseparated in the X-direction by the separation portions 60 having STIstructure. A trench is formed between the above elements that areadjacent in the X-direction. The insulating film is buried in thetrench.

As shown in FIG. 2B, the charge storage layers 30, the second insulatingfilm 40, and the control gate electrodes 50 are separated in theY-direction by the interlayer insulating film (dielectric film) 70.

The charge storage layer 30 is surrounded by the insulator, and is notelectrically connected to anywhere. The electron stored in the chargestorage layer 30 is not released from the charge storage layer 30 andthe electron is not injected into the charge storage layer 30 even whenthe power supply is OFF. The semiconductor memory device (semiconductordevice) of the embodiment is a nonvolatile semiconductor memory devicethat can retain the data without the power supply.

The charge storage layer 30 may have many trap sites that trap chargeinside an insulative film. Such a charge storage layer 30 may include asilicon nitride film.

The control gate electrode 50 is provided on the upper surface of thecharge storage layer 30 with the second insulating film 40 interposed.As shown in FIG. 2A, the portion 50 a of the control gate electrode 50is provided between the adjacent charge storage layer 30 in theX-direction. The second insulating film 40 is provided between theportion 50 a of the control gate electrode 50 and the side surface ofthe charge storage layer 30.

The control gate electrode 50 faces to the upper surface and the sidesurface of the charge storage layer 30 with the second insulating film40 interposed. The control gate electrode 50 faces to the upper surfaceof the charge storage layer 30, and faces to also the side surface ofthe charge storage layer 30. This increase an opposing area of thecontrol gate electrode 50 and the charge storage layer 30, and increasea capacitance between the control gate electrode 50 and the chargestorage layer 30. The strong capacitance coupling between the controlgate electrode 50 and the charge storage layer 30 enhances the writeefficiency and the erase efficiency.

As shown in FIG. 1, the memory cell MC is arrayed at the intersection ofthe control gate electrode 50 and the semiconductor region 11. Thememory cell MC includes the semiconductor region 11, the firstinsulating film 20, the charge storage layer 30, the second insulatingfilm 40, and the control gate electrode 50. One memory cell MC includesone charge storage layer 30 that is provided at the intersection of thecontrol gate electrode 50 and the semiconductor region 11, and providedbetween the control gate electrode 50 and the semiconductor region 11.In the example shown in FIG. 1, the plurality of memory cells MC arearrayed in a matrix in the X-direction and the Y-direction parallel tothe major surface of the substrate 10.

The memory cell array 1 of the embodiment includes, as shown in FIGS. 1,2A and 2B, a first memory cell MCa and a second memory cell MCb. Each ofthe first memory cell MCa and the second memory cell MCb includes thesemiconductor region 11, the first insulating film 20, the chargestorage layer 30, the second insulating film 40, and the control gateelectrode 50 as referred to above. In the following description, theelements of the first memory cell MCa and the second memory cell MCb maybe distinguished by reference numerals and signs. The reference sign “a”is added to the reference numeral or sign of the element of the firstmemory cell MCa. The reference sign “b” is added to the referencenumeral or sign of the element of the second memory cell MCb.

According to the embodiment, a coupling ratio (first coupling ratio) ofthe first memory cell MCa is different from a coupling ratio (secondcoupling ratio) of the second memory cell MCb.

The coupling ratio CR is represented by the first capacitance C_(tnl)between the semiconductor region 11 and the charge storage layer 30, andthe second capacitance C_(ipd) between the charge storage layer 30 andthe control gate electrode 50. For example, the coupling ratio CR is theratio of the second capacitance C_(ipd) to the capacitance(C_(tnl)+C_(ipd)) viewed from the charge storage layer 30. The couplingratio CR is calculated by the following equation (1).

CR=C _(ipd)/(C _(tnl) +C _(ipd))  (1)

In the embodiment, the coupling ratio of the first memory cell MCa isdifferent from the coupling ratio of the second memory cell MCb bychanging the dielectric constant of the material of the secondinsulating film 40 a of the first memory cell MCa and the dielectricconstant of the material of the second insulating film 40 b of thesecond memory cell MCb. For example, the material of the secondinsulating film 40 b of the second memory cell MCb contains a majorelement different from a major element contained in the material of thesecond insulating film 40 a of the first memory cell MCa.

For example, the high-k material such as hafnium oxide (HfO₂) is used asthe second insulating film 40 a of the first memory cell MCa. The secondinsulating film 40 a may be, for example, a silicon nitride film, or aninsulating film containing hafnium aluminate.

When the material of the second insulating film 40 a of the first memorycell MCa is hafnium oxide, for example, hafnium silicate (HfSiO), orhafnium oxide doped with silicon is used as the material of the secondinsulating film 40 b of the second memory cell MCb.

When the material of the second insulating film 40 a of the first memorycell MCa is silicon oxynitride, for example, aluminum silicatecontaining nitrogen, or silicon oxynitride doped with aluminum is usedas the material of the second insulating film 40 b of the second memorycell MCb.

When the material of the second insulating film 40 a of the first memorycell MCa is an insulating film containing hafnium aluminate, forexample, an insulating film containing hafnium aluminate having analuminum concentration higher than an aluminum concentration in thesecond insulating film 40 a of the first memory cell MCa is used as thematerial of the second insulating film 40 b of the second memory cellMCb.

The second insulating film 40 a of the first memory cell MCa is notlimited to the above example. The insulating material having changeabledielectric constant by doping an element not contained in the secondinsulating film 40 a or an element not major element of the secondinsulating film 40 a is used as the material of the second insulatingfilm 40 a.

The material having the changed dielectric constant is used as thematerial of the second insulating film 40 b of the second memory cellMCb.

The change of the dielectric constant of the second insulating film 40between the charge storage layer 30 and the control gate electrode 50changes the second capacitance C_(ipd) between the charge storage layer30 and the control gate electrode 50. According to the above equation(1), the coupling ratio CR of the first memory cell MCa can be differentfrom the coupling ratio CR of the second memory cell MCb.

According to the embodiment, the first memory cell MCa and the secondmemory cell MCb having the coupling ratio CR different from the couplingratio CR of the first memory cell MCa are formed on the same substrate10. The first memory cell MCa and the second memory cell MCb having thecoupling ratio CR different from the coupling ratio CR of the firstmemory cell MCa are included in one chip.

The number of the first memory cell MCa and the second memory cell MCb,the arrangement of the first memory cell MCa and the second memory cellMCb on the substrate 10 are arbitrarily configured. FIG. 3 shows oneexample of the arrangement of the first memory cell MCa and the secondmemory cell MCb. In FIG. 3, the first memory cell MCa and the secondmemory cell MCb are alternately arranged in the X-direction, and thefirst memory cell MCa and the second memory cell MCb are alternatelyarranged in the Y-direction. FIG. 3 is a schematic view of the memorycell array 1 of the embodiment viewed from the X-direction or directlyabove.

The coupling ratio CR defines the voltage Vfg applied to the chargestorage layer 30 by the control gate electrode 50 to which the voltageVcg is applied. The higher coupling ratio CR increases the writeefficiency and the erase efficiency of the data to the memory cell MC.The coupling ratio CR is one of the parameters characterizing theperformance of the memory cell MC. According to the embodiment, thememory cell MCa and the memory cell MCb having different characteristicseach other are provided on one substrate 10 or in one chip.

Next, a method for manufacturing the semiconductor memory device of theembodiment will now be described.

FIGS. 4A to 6B, and 8A to 9B are schematic views showing a method formanufacturing the semiconductor memory device of the embodiment. Inthese figures, FIG. A corresponds to a part of A-A′ section in FIG. 1,and FIG. B corresponds to a part of B-B′ section in FIG. 1.

FIGS. 4A and 4B show a state in which the first insulating film 20, thecharge storage layer 30, and the separation portion 60 are formed on thesubstrate 10.

First, the first insulating film 20 is formed on the substrate 10. Andthen a first polysilicon film 31 is formed on the insulating film 20.

The first polysilicon film 31 and the insulating film 20 are etched inseries by RIE method using a mask not shown. The first polysilicon film31 and the insulating film 20 are divided in the X-direction. And thenthe exposed region of the substrate 10 is etched to form a trench. Thefin-shaped semiconductor region 11 is formed between the adjacent thetrenches in the X-direction.

The insulating film, for example, the silicon oxide film is buried inthe trench and the separation portion 60 is formed.

The second polysilicon film 32 is deposited on the first polysiliconfilm 31 and the separation portion 60. The first polysilicon film 31 andthe second polysilicon film 32 are included in the charge storage layer30.

And then the second polysilicon film 32 on the separation portion 60 isselectively removed, for example, by RIE method using a mask not shown.The plurality of second polysilicon films 32 are separated in theX-direction with the trench 61 interposed between the second polysiliconfilms 32.

Next, as shown in FIGS. 5A and 5B, the second insulating film 40 isformed on the second polysilicon film 32. The second insulating film 40is formed also on the side surface exposed in the trench 61 of thesecond polysilicon film 32. The second insulating film 40 is formedconformally along the side surface and the upper surface of the secondpolysilicon film 32.

For example, the hafnium oxide (HfO₂) film is formed as the secondinsulating film 40 by atomic layer deposition (ALD) method.

After depositing the second insulating film 40, the dielectric constantof the area of the part of the second insulating film 40 is changed.Here, the dielectric constant of the second insulating film 40 in thearea corresponding to the second memory cell MCb is changed. Accordingto the embodiment, the dielectric constant of the second insulating film40 of the second memory cell MCb is changed by implanting silicon (si)selectively into the second insulating film 40 of the second memory cellMCb. The silicon is implanted by ion implantation method. As shown inFIGS. 6A and 6B, the area in which the silicon is not implanted, thatis, the first memory cell MCa is covered with the mask M1.

After depositing the material film of the mask M1 on the secondinsulating film 40, the predetermined opening pattern is formed in thematerial film. The mask M1 is, for example, a resist film itself, or afilm patterned using a resist film. Here, the opening portion MO isformed in the area corresponding to the second memory cell MCb.

FIG. 7 shows the example of the opening pattern of the mask M1 usedforming the memory cell array 1 shown in FIG. 3. The memory cell MCahaving high coupling ratio CR, and the memory cell MCb having lowcoupling ratio CR are alternately arranged in the memory cell array 1.As shown in FIG. 7, the opening portion MO of the mask M1 is formed inthe area corresponding to the memory cell MCb having low coupling ratioCR.

The silicon is implanted into the second insulating film 40 exposed inthe opening portion MO by ion implantation method. The dose amount ofthe silicon is, for example, 1×10¹⁴ to 1×10¹⁶ atom/cm².

The silicon is not implanted into the second insulating film 40 of thearea covered with the mask M1. The second insulating film 40 of the areadoped with the silicon becomes a hafnium silicate film. The dielectricconstant of the hafnium silicate film is lower than the dielectricconstant of the second insulating film 40 (hafnium oxide film) of thearea not doped with the silicon. Or, the second insulating film 40 ofthe area doped with the silicon contains silicon at a higherconcentration than the second insulating film 40 of the area not dopedwith the silicon, and have a dielectric constant lower than that of thesecond insulating film 40 of the area not doped with the silicon. Afterimplanting the silicon, the mask M1 is removed.

After removing the mask M1, as shown in FIGS. 8A and 8B, the controlgate electrode 50 is formed on the second insulating film 40.

First, a polysilicon film 51 is formed. As shown in FIG. 8A, a portionof the polysilicon film 51 is formed also in the trench 61 between theadjacent second polysilicon films 32 in the X-direction. A metalsilicide film 52 is formed on the polysilicon film 51. The polysiliconfilm 51 and the metal silicide film 52 are included in the control gateelectrode 50.

As shown in FIG. 8B, the control gate electrode 50, the secondinsulating film 40, and the charge storage layer 30 are selectivelyetched to expose the first insulating film 20, and a plurality of cellseparating trenches extending in the X-direction are formed. The controlgate electrode 50, the second insulating film 40, and the charge storagelayer 30 are divided into plural parts in the Y-direction by the cellseparating trenches.

Next, an n-type impurity ion is implanted into the surface of thesemiconductor region 11 through the gate insulating film 20 exposed inthe cell separating trench. The n-type impurity ion implanted into thesurface of the semiconductor region 11 is, for example, arsenic ion orphosphorus ion. The interlayer insulating film 70 is formed in the cellseparating trench by plasma CVD method. And then a contact (not shown)connected to the semiconductor region 12 is formed in the interlayerinsulating film 70.

In the above embodiment, after forming the second insulating film 40,before forming the control gate electrode 50, the ion is selectivelyimplanted into the second insulating film 40. However, the method formanufacturing the semiconductor memory device of the embodiment is notlimited to the above method. For example, after forming the polysiliconfilm 51 of the control gate electrode 50, before forming the metalsilicide film 52, the silicon ion may be implanted into the secondinsulating film 40 through the polysilicon film 51.

Also in this instance, as shown in FIGS. 9A and 9B, the ion isselectively implanted with covering the region where the ion is notimplanted with the mask M1. The ion, which has higher energy than energyfor the case of ion implantation before forming the polysilicon film 51,penetrates through the polysilicon film 51 and is implanted into thesecond insulating film 40.

The memory cell array 1 including the plurality of memory cells MC mayhave three or more different coupling ratios.

The three or more different coupling ratios are configured by three ormore different materials of the second insulating film 40. This isachieved, for example, by the difference of the dose amount of thesilicon ion into the second insulating film 40. For example, as shown inFIGS. 10A and 10B, a plurality of regions having different dose amountare formed in the second insulating film 40 by repetitive ionimplantation using a mask while an opening area is changed.

For example, after the first ion implantation of the silicon using themask M1 shown in FIG. 10A, the area of the opening portion MO of themask M1 is spread, or the number of the opening portion MO is increased.And then the second ion implantation of the silicon is performed usingthe mask M1 shown in FIG. 10B.

The similar method described above is applicable to the secondinsulating film 40 having a material containing aluminum oxide.

As described above, according to the method for manufacturing thesemiconductor memory device of the embodiment, the memory cells MCincluding the second insulating film 40 having different dielectricconstant can be formed on one substrate 10 by only the additional ionimplantation step with the mask. The memory cells MC including thesecond insulating film 40 having different dielectric constant havedifferent coupling ratio CR and different characteristics. Therefore,according to the method for manufacturing the semiconductor memorydevice of the embodiment, the memory cells MC having differentperformance can be obtained on one substrate 10 without changing thesize of the memory cells MC (height or width of the charge storage layer30). According to the embodiment, the dielectric constant of the secondinsulating film 40 can be changed by the ion implantation or not. Thismakes it possible to obtain the memory cells MC having differentperformance on one substrate 10 at low cost.

It is not limited to determining the coupling ratio for each memory cellMC in the memory cell array 1. As shown in FIG. 11, the coupling ratiomay be determined for an area including the plurality of memory cellsMC. Here, one memory cell array 1 including an area RGh having a highcoupling ratio CR and an area RGI having a low coupling ratio CR isexemplified. The area RGh includes the plurality of first memory cellsMCa, and does not include the second memory cell MCb. The area RGIincludes the plurality of second memory cells MCb, and does not includethe first memory cell MCa.

A plurality of memory cell arrays 1 may be formed in one chip, and thecoupling ratio may be determined for the memory cell array 1. That is,the one-chip semiconductor memory device (memory chip) includes a firstmemory cell array including the plurality of first memory cells MCa andnot including the second memory cell MCb, a second memory cell arrayincluding the plurality of second memory cells MCb and not including thefirst memory cell MCa.

As described above, the coupling ratio CR is determined according to theequation (1). As shown the following equation (2), the coupling ratio CRis a coefficient for calculating a voltage Vfg applied to the chargestorage layer 30 from a voltage Vcg applied to the control gateelectrode 50.

Vfg=CR·Vcg  (2)

The voltage Vcg (control voltage) applied to the memory cell MC atwriting and erasing is different depending on the coupling ratio CR ofthe memory cell MC. The memory cell having a higher coupling ratio CRmay have a lower control voltage. The control voltage Vcgh of the secondmemory cell MCb having lower coupling ratio CR is higher than thecontrol voltage Vcgl of the first memory cell MCa having higher couplingratio CR.

If the same writing voltage Vcg is applied to the second memory cell MCbas the writing voltage Vcg of the first memory cell MCa, charge may notbe injected to the charge storage layer 30 of the second memory cellMCb. That is, data may not be written to the second memory cell MCb. Ifthe same erasing voltage Vcg is applied to the second memory cell MCb asthe erasing voltage Vcg of the first memory cell MCa, charge may not bereleased from the charge storage layer 30 of the second memory cell MCb.That is, data may not be erased from the second memory cell MCb.According to the semiconductor device of the embodiment, the CRdifference can determine 0/1 of the first memory cell MCa and the secondmemory cell MCb in one operating voltage by properly setting the voltageVcg.

The area RGh including the first memory cell MCa can be used as arewritable memory area and the area RGI including the second memory cellMCb can be used as a non-rewritable read only memory (ROM) area with thecontrol voltage lower than the above Vcgh and being equal to the aboveVcgl or higher than the above Vcgl. Before shipment of the product, datacan be written to the second memory cell MCb with the control voltagebeing equal to the Vcgh or higher than the Vcgh. According to thesemiconductor memory device of the embodiment, different two kinds ofmemory areas can be formed in one chip (on one substrate 10) withoutcomplex manufacturing process and changing the memory size.

Further, according to the semiconductor memory device of the embodiment,the data stored in the area RGI used as the ROM area can be rewrittenonly by changing the control voltage to the Vcgh. It is required to makea photomask when changing the stored data in the general ROM mask. Inthe embodiment, the stored data can be rewritten with the controlvoltage. This reduces costs of development and manufacturing.

Further, according to embodiment, writing/eracing characteristics can bechanged for each memory cell MC. This allows the use as ROM storing datawith inhibiting the writing to the predetermined area or entire area.

In that case, data may be programmed depending on the ion implantationor not with a mask M1 made according to the user's ROM code. That is,“0” or “1” is determined depending on the ion implantation or not. Asshown in FIG. 12, the ion is implanted into the second memory cell MCbcorresponding to the opening portion MO of the mask M1 and the data “1”is programmed in the second memory cell MCb. The ion is not implantedinto the first memory cell MCa corresponding to the area other than theopening portion and the data “0” is programmed in the first memory cellMCa.

FIG. 13 is a schematic plan block diagram of a semiconductor device ofanother embodiment.

The semiconductor device is, for example, a micro controller unit (MCU)8. The MCU 8 includes a memory portion 81, a memory portion 82, a logiccircuit portion 83, a digital-analog converter (DAC) portion 84, ananalog-digital converter (ADC) portion 85, and a peripheral circuitportion 86.

The memory portion 81, the memory portion 82, the logic circuit portion83, the digital-analog converter (DAC) portion 84, the analog-digitalconverter (ADC) portion 85, and the peripheral circuit portion 86 areformed on the same substrate with one-chipped structure. Or the memoryportion 81, the memory portion 82, the logic circuit portion 83, thedigital-analog converter (DAC) portion 84, the analog-digital converter(ADC) portion 85, and the peripheral circuit portion 86 are formed asseparate chips. These chips are mounted on an interposer withone-packaged structure.

The memory portion 81 corresponds to the above semiconductor memorydevice of the embodiment, and includes a data storage area 81 d and acode storage area 81 c.

The coupling ratio of the memory cell MC included in the data storagearea 81 d may be different from the coupling ratio of the memory cell MCincluded in the code storage area 81 c. For example, the data storagearea 81 d may be made up of the first memory cell MCa, and the codestorage area 81 c may be made up of the second memory cell MCb.

In that case, in the same manner as the above embodiment, the dielectricconstant of the second insulating film 40 may be change by the ionimplantation in the manufacturing process of the memory portion 81. Thecoupling ratio of the memory cell MC included in the data storage area81 d may be different from the coupling ratio of the memory cell MCincluded in the code storage area 81 c by the change of the dielectricconstant of the second insulating film 40.

For example, a program executed by the logic circuit portion 83 isstored in the code storage area 81 c. For example, a data controlled bythe logic circuit portion 83 is stored in the data storage area 81 d.The motor, the electronic device, the vehicle and others are controlledby the logic circuit portion 83.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising: forming a first insulating film, a charge storagelayer on the first insulating film, and a second insulating film on thecharge storage layer above a substrate; and changing a dielectricconstant of an area of a part of the second insulating film.
 2. Themethod according to claim 1, further comprising: forming a controlelectrode on the second insulating film after the changing of thedielectric constant of the area of the part of the second insulatingfilm.
 3. The method according to claim 1, further comprising: forming acontrol electrode on the second insulating film before the changing ofthe dielectric constant of the area of the part of the second insulatingfilm, and after the forming of the second insulating film.
 4. The methodaccording to claim 1, wherein the changing the of the dielectricconstant includes doping a first element into the area of the part ofthe second insulating film after the forming of the second insulatingfilm.
 5. The method according to claim 4, wherein the second insulatingfilm comprises hafnium oxide, and the first element is silicon.
 6. Themethod according to claim 4, wherein the second insulating filmcomprises silicon oxynitride, and the first element is aluminum.
 7. Themethod according to claim 4, wherein the first element is implanted intothe area of the part of the second insulating film by an ionimplantation method.
 8. A method for manufacturing a semiconductordevice, comprising: forming a first insulating film on a substrate;forming a charge storage layer on the first insulating film; forming asecond insulating film on the charge storage layer; and changing adielectric constant of a region of the second insulating film by dopingthe region with a first dopant.
 9. The method according to claim 8,further comprising: forming a control electrode on the second insulatingfilm.
 10. The method according to claim 9, wherein the control electrodeis formed on the second insulating film after the changing of thedielectric constant of the region of the second insulating film.
 11. Themethod according to claim 9, wherein the control electrode is formed onthe second insulating film before the changing of the dielectricconstant of the region of the second insulating film.
 12. The methodaccording to claim 8, wherein the changing the of the dielectricconstant of the region by doping includes an ion implantation process.13. The method according to claim 8, wherein the second insulating filmcomprises hafnium oxide, and the first element is silicon.
 14. Themethod according to claim 8, wherein the second insulating filmcomprises silicon oxynitride, and the first element is aluminum.
 15. Themethod according to claim 8, wherein the substrate is a siliconsubstrate.